Fin Field Effect Transistors (FinFETs) are increasingly used in a variety of applications due to their faster switching speed, higher current density and better control of short channel effects over conventional transistors. In a typical FinFET, the channel is provided within a semiconductor fin. The fin generally comprises a single-crystalline semiconductor material with a substantially rectangular cross-section. The fin usually has a height greater than its width, so as to achieve a relatively higher on-current per unit area.
While providing improved performances over conventional Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), FinFETs, however, introduce some design challenges. Specifically, the conventional MOSFETs have almost no limit on the device width, while the FinFETs generally comprise respective fins having a substantially same height. In other words, for control of the on-current and the off-current of transistors, the conventional MOSFETs provide two parameters, the width W and the length L of the channel, but the FinFETs provide only one parameter, the length L of the channel, because the height of the fin and thus the width of the cannel is fixed for all the FinFETs. Therefore, for a given transistor length L, which defines a ratio of the on-current to the off-current, the amount of the on-current from an individual fin is fixed.
However, transistors with different on-currents are often required in high performance Integrated Circuits. One such example is a 6-transistor Static Random Access Memory (SRAM) cell, wherein a ratio of the on-current of a pull-down transistor to the on-current of a pass gate transistor (that is, the β ratio) needs to be kept close to 2 for optimal performances of the SRAM cell.
FIG. 1 is a top view showing a conventional 6-transistor SRAM cell by way of example. As shown in FIG. 1, on a semiconductor substrate, active regions 103, gate electrodes 104 and a first level of metal wiring 105 are provided. The SRAM cell includes 6 transistors: a first pull-up P-type Field Effect Transistor (PFET) 110, a first pull-down N-type Field Effect Transistor (NFET) 120, a first pass gate NFET 130, a second pull-up PFET 111, a second pull-down NFET 121, and a second pass gate NFET 131. Here, the first pull-down NFET 120 and the corresponding first pass gate NFET 130 have respective active regions of different widths, to keep the β ratio around 2. Further, the width ratio of the widths for pull-down NFETs 120 and 121 to the pull-up PFETs 110 and 111 is also around 2, so as to give a current ratio (the γ ratio) of the pull-down NFETs 120 and 121 to the pull-up PFETs 110 and 111 around 4.
Typically, FinFETs comprise respective fins having a substantially same height. This is because the physical heights of the fins in different FinFETs need to be maintained the same to facilitate lithographic patterning of the fins. Furthermore, unlike conventional MOSFETs, an increase in the physical widths of the fins does not result in a corresponding increase in the channel width (or an increased current), because the channel is on the sidewalls of the respective fins. Therefore, to form a 6-transitor SRAM cell by means of FinFETs, some measures must be taken to maintain the β ratio of about 2 and/or the γ ratio of about 4.
A first solution is to use two fins for one pull-down NFET and only one fin for one pass gate NFET. This results in an increased layout area for the SRAM cell. A second solution is to weaken the pass gate NFETs by making the channel length longer. Specifically, the channel length can be made longer by making gate electrodes for the pass gate NFETs wider, for example. As a result, the on-current is reduced. Also, this results in an increased layout area for the SRAM cell. A third solution is to weaken the pass gate NFETs by reducing the height of the fins. This will not increase the layout area for the SRAM cell, because only the vertical dimension is changed. However, presently, there is no efficient way to change the fin height.
Therefore, there is a need for a SRAM cell and a method for manufacturing the same, wherein FinFETs constituting the SRAM cell can comprise respective fins having different heights.